A 138 Mbps jitter based power efficient true random number generator

This paper introduces the design and implementation of True Random Number Generator (TRNG) based on clock jitter. The design extracts jitter from asynchronous type ring oscillator for enhanced randomness. The proposed design is implemented by considering 30 ring oscillators (RO) with a high-frequency divider block (designed by T-FF followed by DFF to address setup and hold time problem) and sampling block followed by a shifter. The design utilizes fewer resources yielding hardware redundancy and enhances the level of randomness. This TRNG has been designed and validated using Artix-7 FPGA. Power dissipation and speed have been obtained as 0.5mW and 138 Mbps respectively. The generated random bit stream has also been sampled and converted to a binary format in MATLAB and tested through the DIEHARD statistical test suite for validation. The obtained binary sequences passed all tests successfully.