Semi-empirical law for fatigue resistance of redistribution layers in chip-scale packages

In this work we present a semi-empirical law for the fatigue resistance of redistribution layers (RDLs) in chip-scale packages. Fatigue of the copper RDL leads to cracks in the RDL stack, which might eventually propagate into the die causing catastrophic failure. Several test vehicles, that show this failure mode during temperature cycling tests, have been simulated. The computed accumulated inelastic strain energy density in the RDL at the failed location shows a power-law dependence with the onset of fail. The results show that the onset of fail does not scale with the package dimensions, as the RDL design itself plays a significant role. Furthermore, the design of the PCB is shown to have a dominant influence as well.To substantiate these findings, test coupons consisting of copper traces on silicon wafers were subjected to mechanical cycling, but showed significantly more fatigue resistance than RDL traces in actual applications. Therefore, we conclude that the semi-empirical law can be used for predictive modeling of the onset of RDL fail, only if a representative pool of test vehicles has been considered. More fundamental research is still needed to gain a complete understanding of the failure mechanism.