On the impact of on-chip inductance on signal nets under the influence of power grid noise

It has been well recognized that the impact of on-chip inductance on some critical nets, such as clock nets, is significant and can not be ignored in delay modeling for these nets. However the impact of on-chip inductance on signal nets in general is still not well understood. We present results of analyzing inductive effects on signal nets for ultra-deep submicron technologies. The analysis is based on a Al-based 0.18 /spl mu/m CMOS process and a Cu-based 0.13 /spl mu/m CMOS process. The impact of on-chip inductance is shown to be insignificant if we assume a perfect power supply network around the interconnect routes. Otherwise, the impact of on-chip inductance can be significant. Furthermore, the results presented in this paper illustrate the impact of on-chip inductance one would expect from transitioning from an Al-based interconnect technology to a Cu-based interconnect technology.