A Low DelayArchitecture for Logarithmic Multiplication

Scope for advancements in Digital Signal Processing (DSP) applications is going to have an exponential growth in the near future. Digital filters and other devices have multiplication as the primary operation. The overall fastness of any application is dominated by the speed of multiplication. It is also necessary to decrease the delay and complexity of the circuit. In this work, the primary objective is to design efficient multiplication architecture for logarithmic operation. The efficiency is quantified by the amount of delay incurred. It is compared with Improved Operand decomposition (IOD) technique. The entire work is simulated in Modelsim 10.4a. Accuracy of the proposed technique is computed using Python. Synthesis is performed using Vivado2014.4. The hardware targeted is Basys-3Artix-7 Board. The proposed design yields 11.18% less delay than the IOD technique.