A DRAM-friendly priority queue Internet packet scheduler implementation and its effects on TCP

To meet various latency requirements for network applications, latency aware packet schedulers that respect per-packet deadlines requested by end systems, such as least slack-time first (LSTF), have emerged. Even though latency aware schedulers are beneficial, few issues remain. First, it is not compatible with best-effort networks, such as the Internet, because of infinite buffer delays by keeping every packet without discarding even in congestion. Second, its implementation is challenging with increasing network bandwidths due to memory device restrictions, i.e., DRAM access latencies. For the congestion issue, we presented earliest deadline first with reneging (EDFR), which can be applied to best-effort services by taking advantage of its packet drop feature. This paper discusses EDFR scheduler implementations on FPGA and its impact on TCP stack with real systems. We designed and implemented skip-FIFO based EDFR onto FPGA, which performed to take advantage of DRAM memory bandwidth, such as 75% of the theoretical limit of High Bandwidth Memory (HBM). The TCP behaviors on EDFR were almost unchanged in terms of throughputs and losses, even for coexisting flows requesting different latencies.