A Method to Balance Dynamic Current of Paralleled SiC MOSFETs With Kelvin Connection Based on Response Surface Model and Nonlinear Optimization

Multichip SiC power modules with Kelvin-source connection are popular in applications with large capacity and high switching frequency. However, dynamic current imbalance among paralleled dies due to asymmetric layout limits the available capacity. Thus, this article proposes a method to mitigate the mismatched dynamic current by adjusting the connection points of bonding wires and copper traces. The response surface models and nonlinear constrained optimization algorithms are introduced for the first time to help determine the optimized positions for the connection points. By this method, the dynamic current imbalance can be well suppressed under various working conditions. Besides, the method is cost-efficient and well compatible with the conventional manufacturing technologies because there need no additional efforts but some modifications on bonding wires. At first, the optimization guidelines are obtained after analyzing the mechanism of dynamic current imbalance among paralleled SiC MOSFETs with Kelvin-source connection. Based on the optimization guidelines and response surface models of parasitic inductance, the dynamic current sharing problem can be transformed into a nonlinear constrained optimization issue in mathematics. According to the solution of the mathematic problem, the optimized positions for connection points of bonding wires and copper traces can be determined. Finally, some simulations and experiments are conducted to verify the effectiveness of the proposed method.