A 5-Gb/s Adaptive Digital CDR Circuit With SSC Capability and Enhanced High-Frequency Jitter Tolerance

A 5-Gb/s digital clock/data recovery (DCDR) circuit with spread-spectrum clocking (SSC) capability and enhanced high-frequency jitter tolerance (JTOL) is presented. To track input data with both the frequency offset and the SSC, an integral gain controller is used to adjust an integral gain of the digital loop filter. It enhances the high-frequency JTOL. This DCDR circuit is fabricated in 40nm CMOS process. Its active area is 0.022mm
²
and the power consumption is 9.9mW from a 1 V supply. With a 5-Gb/s PRBS of 2
⁷
-1, the measured rms jitter of the retimed data is 9.47ps. For input data with the frequency offset of ±300ppm and SSC of -5000ppm, the measured minimum high-frequency JTOL is equal to 0.55 UIpp by using the proposed integral gain controller with a bit error rate (BER) <; 10
^-12
.