A Class-D FVF LDO With Multi-Level PWM Gate Control, 280-ns Settling Time, and No Overshoot/Undershoot

A novel class-D flipped voltage follower (FVF) low-dropout (LDO) regulator is proposed and implemented in this paper to supply high load current with fast transient response for sharp load changes. The proposed class-D control generates a multi-level pulse width modulated (MLPWM) signal to the gate of the control transistor that corresponds to the load level. The MLPWM control signal enables wide loop bandwidth and reduces output ripple. The FVF architecture reduces the output impedance and improves the controller efficiency. A novel feed-forward transition-detection path (FFTDP) controls the gate of the power transistor and allows enhanced switching at high loads. The proposed LDO operates with a wide range of input voltages from 1.2V to 1.8V and dropout of 200mV down to 50mV. The implementation responds to load changes from 0-300mA in 7ns with no observed overshoot/undershoot. The output ripple for the LDO is <; 7mV with roughly 2.5mV due to ESR resistance. The LDO achieves FOM
_V
= 1 mV with a current efficiency of 99.93% at maximum load current. The prototype chip is fabricated on 28-nm CMOS technology and the controller occupies 0.004mm
²
.