Design of UART Module using ASMD Technique

Universal Asynchronous Receiver Transmitter (UART) is an integrated circuit, which is commonly included in microcontrollers and it is usually operated at a baud rate of 20Mbps, which is usually achieved by using a clock of 20MHz. Due to its advantages such as high reliability, long-distance range, and low cost, it is widely used in the data communication process, especially in serial communications over a computer or peripheral device serial port. As indicated or hinted by the designation of the term ‘universal’, the format and transmission speeds of data are configurable to achieve the required operating condition(s). FIFO (First-In-First-Out) technique is used to store the data temporarily during high-speed transmissions and it is also used for synchronization. Usually, the data is serially transmitted one by one into the channel. The output is taken at a sampling period of 10 clock cycles and parallel stored as the data arrives. The results obtained from this experiment indicate that the working of the proposed model can be correlated to or is similar to the results obtained from the theoretical approach in the form of frame arrangement and stacking of data. This paper proposes a change in the frame format to involving the microcontroller or microprocessor, which will control the operation of UART based on the extra bit(s) in the frame, to achieve option(s) for power saving. To design such a circuit at a gate level is tedious and consumes a large amount of time due to the increasing complexity of integrated circuit technology, hence the use of hardware description language such as Verilog HDL is becoming popular because it makes it easy to design a circuit of any complexity. Verilog is pretty different from VHDL. Verilog is not as verbose as VHDL, so that is why it is more compact and hardware modeling is better in it than VHDL, even though it has a lower level of programming constructs than VHDL.