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A 2.02–2.87-GHz −249-dB FoM 1.1-mW Digital PLL Exploiting Reference-Sampling Phase Detector | IEEE Journals & Magazine | IEEE Xplore

A 2.02–2.87-GHz −249-dB FoM 1.1-mW Digital PLL Exploiting Reference-Sampling Phase Detector


Abstract:

This letter proposes a low-power reference-sampling digital phase-locked loop (RS-DPLL). Without any need for a power-hungry low-noise buffer, a reference waveform is dir...Show More
Topic: 2020 European Solid-State Circuits Conference

Abstract:

This letter proposes a low-power reference-sampling digital phase-locked loop (RS-DPLL). Without any need for a power-hungry low-noise buffer, a reference waveform is directly sampled by a reference-sampling phase detector exploiting a bottom-plate sampling technique. The sampled voltage error is digitized through a gated amplifier incorporated with an 8-bit SAR-ADC of tiny size resulting in high effective resolution while consuming <; 0.2 mW. The proposed RS-DPLL is implemented in 28-nm CMOS. Despite the limited slew-rate of the input reference waveform, the proposed architecture achieves 355-fs rms jitter and consumes only 1.1 mW. This leads to the integrated phase noise FoM of -249 dB.
Topic: 2020 European Solid-State Circuits Conference
Published in: IEEE Solid-State Circuits Letters ( Volume: 3)
Page(s): 158 - 161
Date of Publication: 09 July 2020
Electronic ISSN: 2573-9603

Funding Agency:


References

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