A 2.02–2.87-GHz −249-dB FoM 1.1-mW Digital PLL Exploiting Reference-Sampling Phase Detector

This letter proposes a low-power reference-sampling digital phase-locked loop (RS-DPLL). Without any need for a power-hungry low-noise buffer, a reference waveform is directly sampled by a reference-sampling phase detector exploiting a bottom-plate sampling technique. The sampled voltage error is digitized through a gated amplifier incorporated with an 8-bit SAR-ADC of tiny size resulting in high effective resolution while consuming <; 0.2 mW. The proposed RS-DPLL is implemented in 28-nm CMOS. Despite the limited slew-rate of the input reference waveform, the proposed architecture achieves 355-fs rms jitter and consumes only 1.1 mW. This leads to the integrated phase noise FoM of -249 dB.