Jitter Optimisation in a Generalised All-Digital Phase-Locked Loop Model

In this brief, we study jitter behavior in an event-driven self-sampled model of an All-Digital Phase-Locked Loop. We provide its steady-state analysis using simulations of a discrete-time model. We show that digital jitter, a function of two control parameters of the model, can be mapped onto a on-dimensional manifold and approximated via a simple function. The latter can be used to perform jitter optimisation under constraints for the control parameters. The verification is done through FPGA measurements and shows excellent agreement with the analytic approximation.