FPGA implementation of digital timing recovery in software radio receiver

This paper describes an implementation of an all-digital timing recovery scheme. Squaring nonlinearity is employed to generate the timing estimate and an IIR is used to extract the spectral component at symbol rate. Hardware design is performed using VHDL and realized in FPGA. The whole design can be fitted into an Altera EPF1OK70 FPGA chip, with 95.5% utilization of logic elements and 22% utilization of memory bits. The implementation exploits features of FPGA, which enable easy implementation of look up table and variable data precision at different nodes.