Performance and Implementation Modeling of Gated Linear Networks on FPGA for Lossless Image Compression

Over recent years, imaging systems have seen explosive increase in resolution. These trends present a challenge for resource-constrained embedded imaging devices. Efficient image compression is essential to reduce bandwidth consumption and to increase the capability of on-board storage. Especially, for imaging systems where information loss is not allowed, for example, in medical, military and remote sensing imaging systems. This paper explores the use of Gated Linear Networks (GLNs) for development of embedded lossless compression systems. GLNs have proved themselves via PAQ archiver series, that have been ranked among the top across several lossless compression benchmarks. We propose an architecture of single neuron GLNs with emphasis on high throughput performance. Proposed architecture is validated by hardware level tests and described by scalable models that allow estimations of both performance parameters and requirements for hardware resources.