Method for Testing and Debugging Flow Formal Specification in Full-Stack Embedded Systems Designs

Modern embedded computing systems (ES) include heterogeneous components connected “horizontally” and “vertically”, and it demands developing individual quality control design flows for each project. This article discusses the problem of formalizing end-to-end testing and debugging processes in full-stack ES designs. An ontology of ES testing and debugging processes from the multi-level organization point of view and a number of models are proposed using a unified representation of testing, verification, validation and debugging problems at various levels of abstraction. This allows to formally specify a testing and debugging flow of an arbitrary ES design with transition systems describing different states of design process. The application of the proposed solutions provides: control of the coverage of system components by verification and validation processes; identification of gaps in the testing and debugging processes; monitoring of the completed verification and validation steps of system components at different levels.