Circulating Current Suppression in Parallel Interleaved 2L VSIs Using Modified CM Offset Based Method During Inductors Mismatch Condition

Parallel interleaved two-level voltage source inverters (VSIs) could be analyzed as a single multilevel VSI and hence, a significance reduction in the grid side voltage and current ripple could be achieved. However, the parallel interleaved VSIs have a major issue of circulating current. The circulating current is mainly composed of two frequency components: high frequency component and low frequency component. The high frequency component is generated due to the instantaneous difference in the common-mode (CM) voltages of the VSIs. While due to inductance value mismatch in the ac side line frequency inductors, a low frequency circulating current also flows in the system. This low frequency component needs to be controlled as it could saturate the CM, coupled, or interphase inductors used for limiting the high frequency component of circulating current. In this article, an analysis is carried out for circulating current during the inductors mismatch condition. A CM offset signal is also proposed to limit the flow of low frequency component of the circulating current. The proposed CM offset is derived in terms of existing CM offset signals, and hence any existing pulsewidth modulation technique could be implemented using the proposed method. Simulation and experimental results show the improvement in the circulating current using the proposed modified offset.