A vector-pipeline DSP for low-rate videophones

We propose a vector-pipeline processor VP-DSP for low-rate videophones, which can encode and decode 10 frames/s of QCIF through a 29.2 kbps low-rate line. We have already fabricated a VP-DSP LSI by a 0.35 /spl mu/m CMOS process. The area of the VP-DSP core is 4.2 mm/sup 2/ works properly at 25 MHz/1.6 V with the power dissipation of 49 mW. Its peak performance is up to 400 MOPS, 8.2 GOPS/W.