The application of high-level synthesis techniques for the generation of pipelined reprogrammable microcontrollers

With the even changing standards for specific applications such as telecommunications and multimedia the hardwired solution has put limits on flexibility near the end of the design cycle. In many case, designers are moving towards programmable solutions such as to balance the ability for late modification with the usual requirements high speed, low cost, and low power. This paper describes an initial set of modifications to an existing architectural synthesis system (AMICAL) targeting the generation of microcoded controllers. The synthesis process begins with a characteristic application for a chosen class and produces an instruction-set based programmable architecture. The designer can then generate both style of architecture, hardwired and programmable, using the same synthesis system and can quickly evaluate the trade-offs of hardware decisions.