Self-Clamping Programming in Narrow-Bridge Floating Gate Cells for Multi-Level Logic Non-Volatile Memory Applications

A new self-converging programming characteristic in a single-poly floating-gate memory cell with full-compatibility to a CMOS logic technology is observed and studied. A uniquely design cell with a narrow-bridging line between two coupling capacitors promotes a localized charging effect at the electron tunneling site, leading to clamping of threshold voltage states. Through this mechanism, the new multi time programmable (MTP) cells exhibit tight threshold voltage distributions for multi-level cells (MLC) operations. Improved cycling reliability and one-shot multi-level programming has been fully demonstrated in this work.