BDD/AOG-based algorithm for multiple error rectification in combinational circuits

This paper presents a new algorithm for multiple error rectification in combinational logic circuits. The method is based on the use of AND/OR graphs and binary decision diagrams. AND/OR graphs are the corner stone of the rectification algorithm, while BDD's are used to build the AND/OR graphs. A completely automated algorithm is presented for tree structured circuits and a semi-automated one for general circuits. The complexity of the algorithm and the execution times are independent of the number of errors.