ESD Robustness of GaN-on-Si Power Devices under Substrate Biases by means of TLP/VFTLP Tests

The robustness of GaN-on-Si power devices subjected to ESD events in Transmission-Line Pulses (TLP) and Very Fast Transmission-Line Pulses (VFTLP) tests has been investigated under different substrate biases. Compared to a grounded substrate, the robustness behavior with higher trigger voltage (V
_t1
) has been observed under negative substrate biases in both TLP and VFTLP measurements. The VFTLP not only increases the Vt1 with less self-heating effect, but also introduces a distinct instability after holding voltage (V
_h
). The failure mechanism is related to hole-accumulated filament formation and buffer traps under different substrate biases. A device simulation has been carried out to probe the physical insight into failure mechanisms.