A 1.8 GHz Instruction Window Buffer

An Instruction Window Buffer (IWB) addresses the challenges in microprocessor designs beyond a GHz. The IWB implements the processor parts for renaming, reservation station and reorder buffer as a unified buffer. Measured results on an experimental chip demonstrate operation of the IWB macros at 1.8 GHz, with the chip at the fast end of the process distribution. The technology is 0.18 /spl mu/m CMOS8S bulk technology with 7 levels of copper interconnect and a 1.5 V supply. The IWB is implemented using static and delayed reset dynamic circuit macros.