Measurement-Based Modeling of Power Module Parasitics with Increased Accuracy

Simulating time-domain applications with multi-chip power modules requires estimating the module's internal package impedances. This is especially true for modules designed with wide band-gap transistors. Traditional parasitic extraction techniques do not satisfactorily address this need, because they generally do not capture the frequency dependence of the interconnect parasitics. Additionally, they cannot estimate the mutual coupling between module terminals, which is commonly used to reduce commutation loop inductance. This paper proposes a new measurement-based modeling procedure that addresses both challenges with the traditional characterization methods. First, it is shown that by gating ON the semiconductors, the semiconductor channel impedance is reduced to its on-state resistance. This increases the package's proportional contribution, which dramatically improves the resulting accuracy and enables inductance estimation across a wide frequency range. Second, by providing a dual system of equations and isolating one impedance term in the half-bridge module, it is shown that the mutual coupling between the DC terminals can be reliably extracted. The proposed methodology is applied to a discrete-packaged SiC MOSFET, and a medium voltage SiC MOSFET half-bridge power module from Cree/Wolfspeed, which incorporates mutual coupling between its DC terminals.