Congestion Estimation Using Various Floorplan Techniques in 28nm Soc Design

Nowadays demand for various electronic gadgets increasing swiftly. These gadgets should be as tiny as possible, consumes less power and provide better efficiency. The technology entitled "Integrated Circuit" has brought revolution in the production of electronics. The ASIC industries-key contributor of electronic systems moving towards the lower technology nodes to satisfy the demand. As the channel length decreases, device size gets decreases and package density increases. This will arise new challenges to designers. This paper present the implementation of back end design flow-PnR flow and analyzation of routing congestion by examine diverse Floorplan approaches and techniques to improve congestion. Congestion reduction is hinged on the improvement of the floorplan. This improvement has global view of congestion over the entire design. Performing congestion analysis of first floorplan approach proposing next placement move. Improving floorplan using Data Flow Analysis and Fly-line analysis, we can improve the consequences of routing congestion. By using partial/hard blockage further optimization can be done.