An Embedded Tracing Debug Implementation for Crossbar Type Bus in Muti-core SoC

In recent years, with the popularity of multi-core structure in embedded system, traditional single-step debug method encounters many insurmountable obstacles in the face of new features of the target system, such as high integration and high real-time performance. For example, it will affect the program behavior of the real-time system, and it is difficult to observe the concurrent behavior in multi-core system. Embedded tracing debug method solves the above difficulties at the cost of increasing the chip area, which has become one of the research directions of debug technology. In order to observe the interaction behavior between the subsystems in a embedded multi-core system, we take the AXI as an example to research the embedded tracing debug technology for the crossbar type bus. In this paper, we first make the detail presentation for the interconnection structure of AXI, and propose an effective approach to trace the crossbar type bus. Then we explore the data path and the control path for embedded bus tracing debug, and the approach to interpret and analyze the trace data stream. As a case study, we implement a multi-core system based on RISC-V processor for simulation verification, and the experimental results show that the bus tracer we designed can trace and restore the behavior of AXI and assist system performance analysis and optimization.