A Junctionless Accumulation Mode NC-FinFET Gate Underlap Design for Improved Stability and Self-Heating Reduction

A novel metal ferroelectric insulator semiconductor (MFIS) -type junctionless accumulation mode (JAM) negative capacitance (NC)-FinFET with reduced self-heating is proposed for the low-power Internet-of-Things (IoT) applications at 7-nm technology node. Using 3-D TCAD simulations, we have varied the gate to source/drain junction overlap length, which shows that increased junction overlap offers reduced gate-induced drain leakage (GIDL) in NC-FinFET. We then show that the proposed JAM NC-FinFET provides superior ON -state current (
${I}_{\text{ON}}$
) to OFF -state current (
${I}_{\text{OFF}}$
) ratio with and without the self-heating effect (SHE). It also gives stable peak transconductance (
${g}_{\text {m}}$
) with and without SHE consideration due to reduced lattice temperature (
${T}_{\text {I}} = 321$
K). A better capacitance matching due to the presence of depletion capacitance (
${C}_{\text {dep}}$
) is also observed, thereby resulting in low-hysteresis NC-FinFET design. The impact of gate metal work function variation on the hysteresis behavior of NC and JAM-NC-FinFET is also reported in this article. Furthermore, we show that the proposed JAM-NC-FinFET offers superior transconductance generation factor (TGF) in comparison with conventional NC-FinFET in the subthreshold region, making it a potential candidate for low-power applications.