An Area Efficient 19.25 GHz to 77 GHz Gilbert Cell Frequency Quadrupler with 55% Shrinked Delay Lines in 130nm SiGe BiCMOS

This paper presents an area-efficient 19.25 GHz to 77 GHz frequency quadrupler for automotive radar applications. To reduce chip area, the delay lines of each doubler stage have been drastically shrunk by means of meandering, slow wave structures, and capacitive loading. Additional circuit techniques were applied to further reduce chip area. Compared to previously published Gilbert cell frequency multipliers the presented quadrupler achieves the shortest electrical length of the delay lines reported so far allowing for compact, low-cost radar transceivers. The chip was implemented in a IHP 130nm SiGe BiCMOS technology (f
_T
/f
_max
=240/340GHz). It dissipates 91.5mW from a 3.3V supply.