Impact of Interface Traps Induced Degradation on Negative Capacitance FinFET

In this work, we investigate the impact of Si-SiO
2
interface traps on the performance of Negative Capacitance FinFET (NC-FinFET), which is a promising emerging technology that integrates a ferroelectric material inside the gate stack to achieve a steep sub-threshold slope. Interface traps induced degradation is one of the major concerns when it comes to reliability, especially in p-type devices. Our investigation is performed using TCAD models calibrated against 14nm production quality pFinFET. It demonstrates that NC-pFinFET, at the same interface trap concentration, always exhibits less degradation than the baseline pFinFET due to the internal voltage amplification provided by the negative capacitance (NC). However, the amplified electric field across the SiO
2
layer within NC-pFinFET due to NC effect leads to a higher interface trap concentration. This, in turn, results in larger degradations (i.e., higher threshold voltage shift and higher ON-current reduction) in NC-pFinFET devices compared to their counterpart pFinFETs.