Fully Printed Vertical Transport Edge FETs for High Power Oxide Electronics

One of the major challenges for printed electronics (PE) that lowers the performance of the solution-processed/ printed field-effect transistors (FETs) and logics are the limited printing resolution, which at best lies in the micrometer range. In this regard, various concepts have been proposed and exercised to overcome the problem; however, the actual demonstration of high On-currents/ channel conductance has been rare. In this context, we have conceived an innovative device architecture that allows easy printing of edge-FETs, with vertical transport of drain currents along a metal-semiconductor junction. In this manner, we have been able to bypass the low printing resolution problem. In the present work, we report fully printed FETs with a top gate architecture, where an extraordinary ON-current of 6 mA (about
$100 \mu\mathrm{A}/\mu\mathrm{m}$
) can be recorded. Such high device currents alongside excellent On/Off ratio
$(> 10^{7})$
and very low variability enable the present technology to be extremely suitable for printed high power electronic applications.