Development of reusable serial FIR filters with reprogrammable coefficients designed for serial dataflow architectures

This paper presents the development of a family of bit-serial FIR filters with dynamically reprogrammable coefficients. The filters are described in standard VHDL, automatically produced by a parameterized software tool. Reusability was verified by synthesizing the HDL code for different ASIC and FPGA platforms. Efficiency was measured by implementation and accurate timing simulation in ALTERA FPGAs. The proposed filters are designed for use in serial data-flow computation.