Study of Temperature Sensitivity on Linearity Figures of Merit of Ge/Si Hetero-Junction Gate-Drain Underlapped Vertical Tunnel FET with heterogeneous gate dielectric structure for Improving Device Reliability

In this work, temperature sensitivity on linearity figures of merit for a heterogeneous gate dielectric based Ge/Si heterojunction vertical tunnel field effect transistor (TFET) with gate-drain underlap structure has been reported. A source pocket is considered in between source and channel for both the structure to enhance the performance of the device. In the same time, consideration of different device engineered architectures which includes gate-drain underlap and heterogeneous gate dielectric (material having higher dielectric constant is placed nearer to the source end) are made to improve sub-threshold performance of the proposed device. The DC performances in terms of I
ON
/I
OFF
and sub-threshold swing are investigated for the proposed device. In addition to this, operating temperature effect on device transfer and output characteristics are thoroughly investigated by varing the temperature from 250 K to 450 K. Subsequently, effect of variation in operating temperature on the linearity figures of merit (FOMs) such as higher order transconductance (g
m2
,g
m3
), VIP2,VIP3,IIP3, and IDM3 are analyzed for different temperature ranging from 250 K to 450 K. The commercially available SILVACO ATLAS
^TM
TCAD simulation tool has been used to analyze the performance of the proposed device.