Methods of Automated Test Solutions Design for VLSI Testing

The article outlines methods for providing automatic test design for testing integrated structures that implement ultra-large integrated circuits (VLSI). An original route for designing test solutions for ultra-large integrated circuits testing is presented. These solutions include a set of functional tests and electrical equipment with a contacting device. The paper provides a description of the original CAD Functional Test Studio (FT Studio), which provides a solution to this problem and operates on the basis of the original object-and-machine-oriented language STeeL (Smirnov Test Electrical Exposition Language). This system allows automating the verification of almost all types of VLSI, the composition of which is determined by the current standard OST B 11.073.012 -87 “Integrated circuits. General and specific specifications.”, including VLSI qualification tests. The proposed method is based on the two-way communication of the VLSI mathematical and topological model implemented in the FT Studio system, supported continuously within a unified information environment, and really provides an automatic process of functional control of integrated structures. FT Studio CAD provides hardware support and multi-platform support for process equipment.