An FPGA based digital radar receiver for soft radar

Field programmable gate arrays (FPGAs) offer much of the flexibility of programmable DSP processors but with performance closer to application specific integrated circuits (ASICs). As a consequence their use is rapidly growing in demanding DSP applications where low power is not critical and high volumes do not justify the high nonrecurring engineering costs of an ASIC. In this paper we present an FPGA implementation of a digital radar receiver on Xilinx Virtex FPGAs for Soft Radar-a reprogrammable radar system exploiting an open-system architecture. The receiver consists of a simple digital downconverter (DDC) and three stages of FIR filtering. Although the filters are quite different, they have been generated from a single parameterised VHDL description. We present the core architecture and the results of the filter and receiver implementation in an FPGA. On an XCV1000-6 we achieve a processing clock rate of 138 MHz for the receiver.