Diameter Scaling of Vertical Ge Gate- All-Around Nanowire pMOSFETs

In this article, vertical Ge gate-all-around (GAA) nanowire pMOSFETs fabricated with a top-down approach are demonstrated. Thanks to optimized dry etching and digital etching, high-performance Ge GAA nanowire pFETs show low subthreshold swing (SS) of 66 mV/dec, small DIBL, and ION/IOFF ratio of >10
⁶
. The impact of nanowire diameter scaling from 65 to 20 nm on the key electrical figures of merit (FOMs) of vertical nanowire devices is investigated. The devices with 65-nm diameters show the highest ION and peak transconductance Gmax due to reduced total resistance Rtot, while the smallest diameter devices yield the largest ION/IOFF ratios and the smallest DIBL due to strong gate electrostatics. The source/-drain asymmetry inherently exists in the vertical nanowire architectures. By swapping the source and drain, electrical FOMs keep the similar trend in diameter scaling. ION, Rtot, and Gmax asymmetry can be attributed to top-bottom contact resistance difference resulting from the doping deactivation effect in small nanowires.