Page Table Compaction for TLB Coalescing

In the traditional page-based memory management scheme, frequent page-table walks degrade performance and memory bandwidth utilization. A translation lookaside buffer (TLB) coalescing scheme reduces the problems by efficiently utilizing TLB and exploiting the contiguity in physical memory. In modern system hardware, it is usual that a memory transaction concurrently accesses multiple data. However, state-of-the-art TLB coalescing schemes do not fully utilize the data-level parallelism inherent in hardware. As a result, performance and memory bandwidth utilization can be degraded because of certain page-table walk overheads. To alleviate the overheads, we propose to conduct the compaction of allocated memory blocks (CAMB) in a page table. The proposed scheme can significantly reduce page-table walks by utilizing the data-level parallelism in hardware and the block-level allocation in operating system. A design, an analysis, a case study, an implementation, and an evaluation are presented. Considering image processing workloads as an example, experiments are conducted. The results indicate the presented scheme can improve performance and memory bandwidth utilization with modest cost.