Characterization of parametric mismatch attributable to plastic chip encapsulation

This paper uses a high-spatial-resolution test structure and associated high-precision data analysis approach to characterize deterministic and random performance changes of semiconductor devices induced by local mechanical stress variations in plastic encapsulated chips. The results quantify substantial systematic effects caused by lead frame mounting and wire bonding as well as subtle random variability occurrences attributable to the spatial distribution of silica particles in the molding compound. The occurrence of these random silica particle effects is proven by comparing results of unprotected chips to results of those that received a chipcoat gel stress buffer layer prior to plastic chip encapsulation.