Test Structures for Noise Reduction of Fully Depleted-Silicon on Insulator p-Type Tunneling FET Using Channel Orientation

The focus of this study was on the effect of channel orientation on tunneling field effect transistors (TFET). The proposed test patterns were rotated basic TFETs built on silicon on insulator substrates. The patterns were rotated in the (210) and (110) directions in the layout of the test setup. The DC characteristics, subthreshold slopes, and noise were measured. The results show that the on-current and subthreshold slope of the TEFTs were improved up to 8.8 times and 49.6%, respectively. The low-frequency noise was also enhanced approximately 100 times. The reason for the improvements appears to be that the reduced effective tunneling length increases tunneling probability.