Investigation of Electrical Characteristics in a Ferroelectric L-Patterned Gate Dual Tunnel Diode TFET

This paper presents a ferroelectric L-patterned gate TFET with heavily doped (p⁺⁺ type) dual tunnel diodes (DTDs), which analyzes the concept of negative capacitance as well as vertical tunneling. The tunnel junction and the channel direction are perpendicular that facilitates a broad area of the tunnel junction. Furthermore, ON current is enhanced due to the introduction of n⁺ pocket. To exaggerate the I_ON/I_OFF ratio, the device architecture is designed systematically by optimizing the ferroelectric and pocket thickness. The cumulated holes are extricated by the tunnel current produced by the DTDs, reducing the kink effect. An enhanced ON current of the order of 10^-5 A/μm with a minimal subthreshold swing (SS) of 29 mV/decade is achieved. The characteristics of the proposed TFET structure is compared with the existing TFET designs, and the proposed design proves to be an appropriate device for high performance and ultra-low-power applications.