Solder joint failure analysis using FEM techniques of a silicon based system-in-package

A silicon-based system-in-a-package (SiP) was designed that integrates all of a desktop computer's high-performance ICs, including CPU, cache memory, memory controller, and Ethernet, USB and ATAPI I/O interfaces. The primary benefits provided by this integration are the ability to operate the backside CPU/cache bus at full frontside speeds, as well as optimized power dissipation and thermal management. The term SiP is used to indicate a level of integration which combines multiple ICs and associated discrete elements into a single package. This particular SiP was configured as an area array package. Viscoplastic finite-element simulation methodologies were utilized to predict ball and bump solder joint reliability for a silicon based, five-chip SiP design under accelerated temperature cycling conditions. Multiple ball and bump configurations consisting of both 63Sn/37Pb eutectic and 90Pb/10Sn high temperature solder balls were investigated. The solder structures accommodate the bulk of the plastic strain that is generated during accelerated temperature cycling due to the thermal expansion mismatch between the various stack-up materials in the SiP. Since plastic strain is a dominant parameter that influences low-cycle fatigue, it was used as a basis for the evaluation of solder structural integrity. This paper discusses the conditions and environment used to physically stress the module. A summary and further suggested work are provided.