Direct digital frequency synthesis of low-jitter clocks

This paper presents a new phase correction technique applicable to phase accumulators that allows them to express arbitrary rational divide ratios such as R=N/M. Compared to existing methods, the technique gives better results in terms of jitter, and it simplifies design and implementation of practical direct digital synthesis circuits. A typical application of the proposed technique is digital television, where combinations of existing standards lead to the need to synchronize exactly a 6.144-MHz audio clock with a 35.46895-MHz video clock. This implies a divide ratio of R=122880/709379.