A low-power CMOS super-regenerative receiver at 1 GHz

A low-power and low-voltage super-regenerative receiver operating at 1 GHz and implemented in a 0.35-/spl mu/m CMOS process is described. The receiver includes a low-noise amplifier, a super-regenerative oscillator, an envelope detector, an AGC circuit with sample/hold function, and a baseband amplifier. The die surface is equal to 0.25 mm/sup 2/. The power consumption is less than 1.2 mW at V/sub DD/=1.5 V. A 100-kHz sawtooth quench signal is used to achieve a rejection of -36 dB at 500 KHz from the central frequency.