High-performance flexible all-digital quadrature up and down converter chip

In this paper, the design of an all-digital quadrature up and down converter with high accuracy and flexible intermediate frequency (IF) settings is presented. The signal up or down conversion is achieved by interpolation and decimation combined with a programmable anti-alias filter to preserve the selected frequency band during the sample rate conversion. This way a high-speed solution with low power consumption is obtained. A novel technique, based on the use of canonic signed digit (CSD) code, was utilized to implement the programmable anti-alias filter structure. The resulting chip fabricated in a 0.5-/spl mu/m CMOS process is capable of handling sample rates up to 160 megasamples per second (MSPS) and is suitable for coaxial access network modem applications.