Single Flux Quantum (SFQ) First-in-First-Out (FIFO) Synchronizers: New Designs and Paradigms

Digital single-flux quantum (SFQ) technology promises to meet the demands of ultralow-power and high-speed computing needed for future exascale supercomputing systems. However, high degrees of variability makes ultrahigh-speed low-skew clock distribution of large-scale SFQ circuits challenging. This article proposes to mitigate this problem by supporting multiple independent SFQ clock domains with the design of reliable clock domain crossing (CDC) circuits. We first show that previously proposed CDC first-in-first-out buffers (FIFOs) are vulnerable to synchronization errors, motivating the need for more robust CDC FIFOs. Inspired by complementary metal-oxide-semiconductor (CMOS) multi-flip-flop FIFO synchronizers, we then present a metastability-resilient SFQ FIFO synchronizer that, simulations show, delivers over a 1000 reduction in logical error rate at 30 GHz. We show that, for a 10-stage FIFO, the Josephson junction area of our proposed design is only 7.5% larger than the nonresilient counterpart. Finally, we propose detailed design guidelines that define the minimal depth of our proposed synchronizers subject to both throughput and burstiness constraints.