Development of serial RapidIO high-speed data transmission based on VPX bus

This paper presents a high-speed data transmission plan based on VPX bus. The aim is to establish a high-speed data transmission structure which could be used for dealing with massive echo data from the PAR (Phased array radar) in the future. The frequency is up to gigahertz so that it is hard to design the PCB which is used for high-speed serial data transmission between the boards. Stable and reliable interconnection between payload boards is a main problem. This paper uses channel simulation method to design the hardware. A channel simulation model is established between high-speed backplane and payload modules. This design extracts key information from channel tub curve and eye diagram, then design the hardware based on channel capacity and bit error rate. This paper designs a dual-channel highspeed serial RapidIO annular communication between payload modules based on VPX bus. Single channel theory transmission rate is 3.125Gbps. And the result shows that the actual speed of dual-channel is up to 540.70MB/s. It's nearly the theory speed of the RapidIO communication protocol.