A Shortest Path Finding Time-Based Accelerator Core With Built-in Gravity Control and Buffer Zone for Smooth 3-D Navigation

A mixed-signal time-based 65-nm application specific integrated circuit is developed for solving shortest-path problems in 3-D. Previous path planning ASICs have been restricted to 2-D maps due to computational complexity or physical architecture limitations. Our time-based, asynchronous, one-shot architecture has been coupled with a novel dual axis interleaving strategy to solve the multidimensional shortest path problem in a simple, energy efficient manner. Additional features include circuit-based solutions for obstacle blockage avoidance and gravity. The efficacy of the proposed ASIC is evaluated on a drone navigation application, 3-D Voronoi diagrams, and a physical optics experiment. The chip is twice as energy efficient as prior 2-D work while containing $5\times $ more vertices and $7.5\times $ additional edge connections.