Fault-tolerant Quantum Implementation of 1-bit and 4-bit Comparator Circuit using Clifford+T-group

Aiming to design a complete Quantum Information Processor (QIP), in this work, we are showing an efficient implementation of fault tolerant quantum comparator circuit. To ensure this fault tolerant property in the design, we have used Clifford+ T-group and also have executed circuit optimization algorithm to contain the cost metrics. In the design phase, initially an optimal 1-bit circuit is formulated and then by integrating 1-bit modules, 4-bit comparator is prepared. Though we have shown only 1-bit and 4-bit circuits but it can be generalized for n-bit design as well. Our proposed design is quite different from existing fault-tolerant comparator models as our circuit is magnitude driven design and can compare magnitude of numbers by encoding the input vector into equivalent binary numbers as well. Towards ensuring improved features in our proposed model, the design is transformed to minimum T - depth based design, which in turn ensures minimum CPU cycles to obtain the first output from the design as well reduces the effect of decoherence. In addition to this, the proposed model has optimal T - count metric to control the circuit overhead. The functional correctness of our design also has been checked using several test patterns.