Design, Analysis and Comparison of PFD Architectures for Fast Locking Frequency Synthesizer

In this work design and analysis of Two Phase Frequency Detector (PFD) architectures have been carried out in SCL 180 nm CMOS technology. Performance of these PFD's are evaluated in terms of delay and power consumption. Supply voltage of 1.8 V is used to optimize the performance. Among the two designed PFD architectures, first PFD is designed using Multithreshold Complementary Oxide Semiconductor (MTCMOS) power gating technique and second is designed by utilizing feed forward reset PFD using external delay cell. First architecture has the advantage of reduced power consumption whereas second architecture is suitable for the design of high frequency and low jitter frequency synthesizers, as it offers very small dead zone. Simulation results display that feed forward PFD is free from dead zone but at the cost of increased complexity in terms of area and power consumption.