A Contention-free, Static, Single-phase Flip-Flop for Low Data Activity Applications

Static flip-flops are basic parts of industrial digital circuits which affect speed and total power consumption. Several static flip-flops have been proposed recently to reduce the large clock related power of the conventional Transmission Gate Flip-Flop (TGFF). Pre-charging is an efficient method to reduce the number of clock transistors and the clock power. Although pre-charging reduces power at higher Data Activities (DA), it is power inefficient at lower DA. The non-pre-charging methods (with or without contention) increase the D-to-Q delay or the power at high DA. In this paper, a fast single-phase contention-free flip-flop is proposed which has a low power consumption when DA is low. This flip-flop is referred as to LLFF (Low-power at Low data-activity Flip-Flop). Simulation results in 65 nm technology show that the proposed flip-flop consumes up to 45% less power compared to recently published flip-flops at low DA, while its D-to-Q delay is comparable.