A 100 KS/s 8–10 bit resolution-reconfigurable SAR ADC for bioelectronics application

A 8-10 bit resolution-reconfigurable SAR ADC for bioelectronics application is proposed. The ADC consists of resolution-reconfigurable binary-weighted capacitive DAC, a two-stage full dynamic comparator, and the resolution-control SAR logic. Simulated in 180 nm CMOS process, the ADC achieves the 49.77/55.65/61.36 dB signal-to-noise and distortion ratio (SNDR) and 67.56/71.94/78.41 dB spurious-free dynamic range (SFDR) at 100 kS/s sampling rate with the power consumption of 0.81/0.91/1.01 μW.