A Speed and Energy Focused Framework for Dynamic Hardware Reconfiguration

The current trends in Integrated Circuits are driven by the best utilization of the rapidly saturating and costly technologies. One of such endeavors is to build a self-adaptive, autonomous or evolving system which is capable of adjusting or rebuilding itself upon self-assessment. In order to come closer to this goal, different components have to be realized to reach to the final shape. These components are reconfigurable hardware systems, algorithms for placement and routing, learning, or optimizing and sensors or ways to track different system performance metrics. This paper focuses on building a framework to enable hardware system reconfiguration flexibility. The framework efficiently maps different applications on hardware and addresses different trade-offs. This is done mainly by introducing two main parts for a dynamic reconfigurable adder trees. The first part focuses on a platform that models adders, generates their performance parameters and analyzes the performance over different workloads. To evaluate the adders, a case study of image processing kernels such as sobel, blur, and sharpening filters are adopted as the analysis workload and translated into their core summation operations. The analysis shows how dataflow is reflected over prefix nodes. The second part focuses on building a hardware layer that offers reconfiguration flexibility which manages to dynamically change adder structure without the need to reprogram the whole FPGA implementation and reprogramming its bitstream. Both parts of the paper shows a promising case study of system optimization with the speed and energy trade-offs considered.