Analysis of Large-Signal Output Capacitance of Transistors Using Sawyer–Tower Circuit

A detailed analysis of the Sawyer-Tower method used in the measurement of large-signal output capacitance ( C_o) of power transistors is presented, followed by important design recommendations to obtain accurate results. Key factors affecting the proper implementation of the technique, such as power amplifier characteristics, load slew rate, reference capacitor ( C_ref), and reverse conduction of the device, are addressed, with accompanying simulation and experimental results for Si, SiC, and GaN devices. A thorough investigation of the selection of C_ref is presented, with a new equation to correctly determine its value for a given voltage swing and output capacitance range of the device under test (DUT). We report that the Sawyer-Tower circuit imposes the DUT to enter steady-state reverse conduction under certain conditions, thus leading to charge-voltage (QV) hysteresis patterns unrelated to C_o. Our analysis reveals that the origin of this phenomenon is related to DUT's leakage current and it could be minimized by the proper selection of excitation frequency. This article intends to provide an effective guide on designing and using the Sawyer-Tower circuit, and to induce further scientific insight on characterizing C_o.